Beach Solutions® EASI Code™ auto-generates correct-by-construction software for significant development and test savings. Automated capture, validation and generation tools for SoC register address maps and device operational information lead to right-first-time system integration and improved IP reuse.
Today’s SoCs typically contain thousands of software programmable registers and the low-level software API for a single register can consist of more than 50 different functions. The problem facing a development team is how to keep code up-to-date, and error-free, while the register address map evolves during development.
EASI Code provides a language-independent graphical application for managing the valid transactions between registers in your SoC. It can be used standalone as a flowchart capture and validation tool, or as part of EASI Tools to increase your chances of being Right First Time.
Upgrade to EASI Code Advanced for document auto-generation.
>> Read the EASI Code Leaflet
Advanced software development
EASI Code accelerates the system integration stage as the manual error-prone integration and software layer tasks are automated. Auto-generation of correct-by-construction ‘SystemC’ and ‘C’ code shortens the software development and test cycle, e.g. register models are available earlier.
Improved efficiency
Dynamic/setup data for memory-mapped objects are held formally in a central EASI Sequence XML database that is globally accessible. No specialized programming knowledge is required as the operational behavior is specified in a logical way. This focuses the process and the focus is on logic and intent rather than language constraints.
The transfer of project information is greatly improved leading to right-first-time designs and better IP reuse.
Software integration and verification is simplified because the manual error-prone creation of register sequences in C is automated.
Major quality improvements
All register sequences are automatically checked and syntax
and semantic errors identified before delivery to provide
a solid foundation for the generation of APIs and test code.
A firmware developer uses EASI Code to auto-generate software for all of the registers and memories in a design. Operational setup or verification sequences are then described e.g. power-on-reset or initialization, and the associated deliverables are auto-generated for transfer within the project team.
Note: EASI Code has a pre-requisite of EASI SoC.
Auto-generate SystemC PV Model
SystemC offers an increase in productivity by further abstraction from an RTL description of the register block. However, there is little advantage in this approach if the SystemC view is yet another manually entered, parallel view of the same registers.
Using the centralized EASI Tools Suite database, EASI Code auto-generates the transaction-level programmer’s view (PV) model in ‘SystemC’ for all address mapped registers and memories for an entire design.
SystemC TLM target
Accelerate system development
The output of the new SystemC PV generator is a functionally accurate memory mapped register model. The auto-generated model would be used:
- By software developers as an accurate and representative model of the memory mapped registers and memories in an IP block, or entire design e.g. for IP block device driver and API development.
- By verification engineers within a testbench to functionally verify an IP block against an equivalent RTL (Register Transfer Level) implementation written in a hardware description language such as Verilog or VHDL.
- By verification engineers to substitute equivalent parts of RTL with a SystemC representation during stages of development of large designs to improve simulation efficiency.
The auto-generated SystemC PV model comprises multiple layers; each layer providing a different way to drive the register and memory model:
- Standard PV interface
The files output by EASI Code provide the ability to drive the auto-generated register and memory model using SystemC via a standard PV TLM interface. This allows designs to be developed using a common abstract interface and then implemented using any bus architectures that adhere to this abstracted interface without the need for recoding.
- Hardware MRB interface
The register and memory model may be auto-generated with an MRB (Memory-mapped Register Block) wrapper and a bus interface component with a simple PVCI interface to
enable the creation of a more rigorous test environment. A HDL wrapper allows the SystemC model to be used in a physical environment, e.g. instantiated in an HDL design as a foreign architecture.
Requires EASI Core Power or EASI SoC Power
to auto-generate the complete HDL description for the MRB
- Direct software interface
The auto-generated register and memory model can be driven directly using SystemC and/or C++ via software functions. An API is auto-generated comprising access functions to read and write to registers and bitfields and get/set functions monitor/modify values directly.
Auto-generate C API
Using the centralized EASI Tools Suite database, EASI Code auto-generates the physical layer API for all address mapped registers and memories in C for an entire design. This means the hardware and software interfaces remain consistent throughout project lifecycle.
Automate error-prone tasks
Auto-generate a comprehensive suite of all legal 8-bit, 16-bit, 32-bit and 64-bit access functions or macros required to access each IP interface in a system. Build libraries to deliver with your optimized or generic IP containing C code to read, write, get and check values from registers, bitfields, enumerations and memories.
In addition, supporting C files are auto-generated for the system:
- Top-level system map file with base address definitions
- Register, bitfield and memory literal definitions
- Enumeration type definitions
- Default macros for accessing memory and IO
Often when you are trying to debug application code it is useful to see when, where and how often level 1 access macros are being used (e.g. for code profiling or debug purposes). To help with this, each access macro/function generated by EASI Code is uniquely numbered and may contain a built-in debug macro that writes the function number to a magic address. In a simulation, this magic address could be a dummy peripheral IP block that converts each function number into a message output during the simulation. The IP block feeds back the output to a PC via an RS232 port etc. The PC could then capture and store the numbers in a file that could be post processed in order to yield a similar message log to that produced during simulation.
Dynamic behavior information capture
EASI Code offers a language-independent graphical data management
tool for configuring and managing the operational software and
verification sequences between registers in an SoC. The powerful
combination of EASI Core and EASI Code allow you to describe
both the static structure and the dynamic behavior of a device. Knowledge of addresses, pointers & masks is no longer required.
Key applications include:
- Complete SoC initialization
- IP setup routines and function libraries
- Interrupt service routines
- Test setups and routines
