Beach Solutions® EASI Core™ provides the tools and utilities necessary to package and deliver an IP block for accelerated integration and subsequent reuse in SoC designs. EASI Core is used standalone to capture and validate IP address-mapped items and interfaces or as part of EASI Tools.

Upgrade to EASI Core Advanced for design document auto-generation. Upgrade to EASI Core Power for RTL auto-generation of the IP block bus interface and register block.

>> Read the EASI Core Leaflet

Key benefits

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Increased productivity

EASI Core provides the foundation for correct-by-construction auto-generation of SoC design and system integration deliverables from a common design register database.

Increased quality

All addressable objects, including imported IP-XACT elements, are automatically checked so that design errors are identified before system integration. Catching discrepancies between domains earlier in the flow prevents error propagation through out the design cycle.

Increased efficiency

IP interface data is held formally in a central XML database that is globally accessible. This means one fact in one place so all development teams work from the same data. Automatically incorporate system level changes at the IP level to accelerate SoC derivative development.

Product description

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EASI Core enables IP core registers, bitfields, enumerations, ports and bus interfaces to be easily captured, managed and validated. Beach Solutions refer to this type of information as static design information. EASI Core is a language neutral solution and no programming knowledge is required to describe the memory-mapped objects. IP data is stored in a central XML repository that is design environment independent.

• IP design data capture
• Specification navigation
• Automated data checking
• SoC memory map comparison
• Generator launch pad

Rapid data capture

• Automatically capture through IP-XACT importer
• Automatically capture through Textual Input Language importer
• Enter manually via an intuitive graphical user interface
• Use pre-populated boilerplate templates for common objects
• Transfer spreadsheet data

>> Read more about Beach Solutions Data Capture.

Graphical navigation of the specification

The graphical IP data management application in EASI Core makes for fast navigation of the database, from an entire collection of IP blocks to a single enumeration, through intuitive mouse clicks. EASI Core has a number of graphical capabilities that facilitate efficient IP design.

Interactive bitfield graphical interface

Bitfield widths are represented graphically when a register is selected and the power-on-reset values are also shown. To assist with identifying bit errors, overlapping bitfields are cascaded vertically and conflicting reset values are visually highlighted. New bitfields are easily created using the graphic and drag & drop is used to move or resize a bitfield.

Interactive address map viewer

The graphical address map viewer utility for an IP block bus slave provides an immediate view of the design by showing where IP block items have been placed in the device's memory map. Items can be moved and deleted within this view and objects can be quickly located by entering a particular address value or name.

Automated data checking

EASI Core contains an automated data checking process with a large and extensible number of Design Rule Checks (DRCs). Design rule checks can be applied at any time during data capture, even before the design is complete. There are over 150 built-in standard IP rules available in EASI Core, which can be modified with EASI Developer Suite. The types of IP block checks are:

• Naming convention conformance e.g. pattern matching, uniqueness
• Memory map address conflicts
• Overlapping bits
• Conflicting attributes, e.g. access mode conflicts, data width conflicts

An intuitive graphical user interface presents the errors, warnings and related information messages from which the user double-clicks straight to the source of issue.

IP quality-stamp

Upon a successful data check, each IP block is watermarked with a digital fingerprint for added security. Generator-specific watermarks identify known good blocks ready for auto-generation with other tools in the Beach Solutions EASI Tools Suite.

Generator launch pad

EASI Core provides the graphical control center for configuring and running Beach Solutions generators. A wizard-based interface guides you through setting generation options and controlling the layout and content of the output design deliverables. A further graphical tool is available to define drilldown trees that mark a set of design objects and apply special behavior at generation runtime, e.g. to exclude internal test registers from the generated output.

SoC memory map comparison

EASI Core includes a utility to report the differences between the register and address values of IP devices in an SoC design. Formally comparing different versions of the common register database ensures that all specification changes are visible and managed as the design evolves. This minimizes the impact of errors downstream.

The difference graphical tool presents a navigation tree view of the definitions contained in the EASI Tools Suite system and IP block databases and visually highlights the differences between the two databases. The ability to single-click straight to the source of the change means that errors are traced and caught at an early stage. This prevents their proliferation through the design process.

Key features

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	EASI Core	EASI Core Advanced	EASI Core Power
IP data management
Centralized IP database based on a language neutral solution
Describe registers and their bits, memories and reserved addresses
Describe bus master and slave interfaces
Place items in a bus slave's memory map
Describe ports for external interfaces
Rapid data creation
The SPIRIT Consortium IP-XACT import
Textual Input Language (TIL) import
Boilerplate templates for common objects
Transfer from spreadsheets
Graphical views
Hierarchical design presentation of IP objects
Software memory map presentation of IP objects
Interactive bitfield graphical interface
Interactive address map viewer
Hide/ rename objects/attributes in the display
IP configuration
Parameterized numeric IP values (overridden in EASI SoC)
DRC rules to check parameters
Data manipulation
Automated method for locating registers
Control default values for new objects
Recursive find & replace
Database objects easily extended
Database information reports
Automatic Design Rule Checks (DRC)
> 150 built-in IP block design rule checks
Graphical presentation of data check results and IP figure of merit
Double-click straight to source of errors
Save report in textual format
IP block database watermarked for security
Documentation auto-generation
Auto-generated HTML IP design document
Auto-generated RTF IP design document
Auto-generated PDF IP design document
Auto-generated MIF IP design document
Auto-generated HTML IP memory map document
Auto-generated RTF IP memory map document
Auto-generated PDF IP memory map document
RTL auto-generation
Verilog/VHDL description of bus logic block (each slave interface)
Verilog/VHDL description of address mapped register block
Verilog/VHDL description of memory interface signals with various configurations
Verilog/VHDL description of address decoder
Verilog/VHDL description of read data multiplexer block
Verilog/VHDL description of MRB top level entity & architecture
Enumerated IP block package file
System address map file
Verilog/VHDL description of IP top level
Simple PVCI interface
Customizable bus logic component
Default AMBA AHB and APB bus logic templates supplied
Parameterized IP with instance based generation
Exclude memory mapped registers from register block (resides in IP)
Support for registered read only registers
Support for external reset sources
Support for internal & external enables
Support for set / clear (sticky) bits & self clear bits
Support for double output stage register/bitfields
Support for making write enable signals available externally
Generation of asynchronous or synchronous reset code
Support for registered read enable decodes
Support for registered read mux output stages
Support for alternative clock and/or alternative reset
Exclude reserved objects
Customization of header & footer
Support for single register with different read address and write address
Disconnect register write output from IP
Generator-specific design rule checks to avoid synthesis errors
IP memory map value comparison
Difference values between two IP block databases
Graphical navigation of difference results
Double-click straight to source of change
Operating system support
Microsoft® Windows® 2000 / Microsoft® Windows XP®
Red Hat Enterprise Linux AS release 3
Sun Solaris Operating Environment 8

EASI Core Advanced

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EASI Core Advanced includes the auto-generation of both printed and web-based documents leading to substantial productivity increases. These automatically generated documents and web views can be updated at the push of a button and then used or distributed as document files or postings to an intranet web site before coding has even started. This easy to use yet powerful update mechanism ensures that all members of a development team are synchronized and use the latest information as they execute their part of the design.

EASI Core Power

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EASI Core Power offers RTL design file auto-generation for each IP block bus interface logic and local decode for every register and embedded memory. Major quality improvements are achieved using auto-generation as bitfield or register address errors are eliminated and specification misinterpretation errors are avoided.

EASI Developer Suite

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EASI Developer Suite (EDS) includes a generator configuration kit used to modify each of the generators for rapid customization of the structure and content of an auto-generated view. This enables the generators to be customized to support proprietary verification and test flows and improves control over the usability and integration of EASI Tools and Generators within your flows. The design rule checks provided with EASI Core can be tailored and extended to enforce internal constraints and policies.