A Power version of the Beach Solutions® EASI Core and EASI SoC products is available that enables the auto-generation of Register Transfer Level (RTL) code to describe the memory mapped registers and bus interface logic for each of the IP cores in a design at the click of a button.

Key benefits

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Significant engineering cost savings

EASI Power makes it easier to build derivative products as the auto-generation of correct-by-construction RTL to interface IP cores with different bus structures maximizes the benefits of reuse.

Reduced risk of integration errors

Auto-generation provides significant design savings as repetitive and error prone design tasks are automated. RTL generation accelerates hardware design resource availability and focuses resources on value-added design work.

Improved design team efficiency

Auto-generate Verilog or VHDL design files and other software and verification views from the same EASI Tools database early in the project to significantly accelerate time to market and enable hardware-software co-design.

Package description

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RTL design file auto-generation

Auto-generate RTL IP block interface code with EASI Power HDL design generators. All output files are generated from the common design database, guaranteeing ensuring data consistency between generated design deliverables. This eases the process of hardware software co-design and final system integration.

The following VHDL/Verilog descriptions are auto-generated for each IP in the design significantly reducing bitfield/register address errors: Bus logic block for each bus slave interface

• Address mapped register block
• Address decoder block
• Data multiplexer block
• Top level entity and architecture (rtl) containing instances of blocks
• Enumerated IP block package/constant file
• System address map file

Target multiple bus standards

Achieve true IP reuse across multiple projects, as IP blocks are output with standard or custom bus interfaces. EASI Power supplies default AHB and APB bus templates, and proprietary bus templates are easily created to automate migration of cores to derivative designs.

Complex register behavior behavior support

EASI Power handles special register behavior by changing how the decoder, register and multiplexer code is created depending on the presence of external and internal reset or clear registers, sticky bits, self clear etc.

Key features

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	EASI Power
RTL auto-generation
Verilog/VHDL description of bus logic block (each slave interface)
Verilog/VHDL description of address mapped register block
Verilog/VHDL description of memory interface signals with various configurations
Verilog/VHDL description of address decoder
Verilog/VHDL description of read data multiplexer block
Verilog/VHDL description of MRB top level entity & architecture
Enumerated IP block package file
System address map file
Verilog/VHDL description of IP top level
Simple PVCI interface
Customizable bus logic component
Default AMBA AHB and APB bus logic templates supplied
Parameterized IP with instance based generation
Exclude memory mapped registers from register block (resides in IP)
Support for registered read only registers
Support for external reset sources
Support for internal & external enables
Support for set / clear (sticky) bits & self clear bits
Support for double output stage register/bitfields
Support for making write enable signals available externally
Generation of asynchronous or synchronous reset code
Support for registered read enable decodes
Support for registered read mux output stages
Support for alternative clock and/or alternative reset
Exclude reserved objects
Customization of header & footer
Support for single register with different read address and write address
Disconnect register write output from IP
Generator-specific design rule checks to avoid synthesis errors