Beach Solutions® EASI SoC™ is a platform package for managing software addressable registers within multi-level hierarchical systems in a System-On-Chip (SoC).

EASI SoC includes all of the features in the EASI Core product.

Many projects suffer later in the design cycle, due to late bug fixes in the hardware that have a significant impact on the software implementation. EASI SoC provides a living interface specification for all members of the project team throughout the development of an SoC.

Upgrade to EASI SoC Advanced for design document auto-generation. With the Power version, EASI SoC auto-generates Register Transfer Level (RTL) code to describe the memory mapped registers and bus interface for each of the IP cores in a design.

>> Read the EASI SoC Leaflet

Key benefits

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Significant engineering cost savings

EASI SoC makes it easier to build derivative products as the system view is constructed from proven IP blocks. Auto-generation of correct-by-construction RTL maximizes the benefits of reuse.

Reduced risk of integration errors

All system interfaces are automatically checked so that the entire SoC register address map is validated and integration errors are caught quickly.

EASI SoC auto-generation provides significant design savings as repetitive and error prone design tasks are automated. RTL generation accelerates hardware design availability and focuses resources on value-added design work.

Improved design team efficiency

Entire SoC address map and system interconnections are stored in a central xml database that is globally accessible. Auto-generate Verilog or VHDL design files early in the project to significantly accelerate time to market and enable hardware-software co-design.

Product description

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EASI SoC is a platform package for managing software addressable registers within multi-level hierarchical systems in a System-On-Chip (SoC). Platform connectivity data is stored in a central XML repository that is design environment independent. EASI SoC processes are neutral and not tied to any bus architecture or design flow.

• Interface-based data capture
• Configurable IP
• Automated data checking

Interface-based data capture

Use EASI SoC’s intuitive graphical user interface to quickly assemble multi-layer systems with infinite hierarchy and multiple interconnecting buses that locate memory-mapped components with physical and bus interfaces. Powerful graphical utilities provide immediate visualization and navigation of the entire system address map to assist with integration.

Rapid data capture

EASI SoC includes automated utilities to speed up the capture phase of design.

• Pre-populated boilerplate templates for common objects
• Copy and paste from spreadsheets
• Single-click to promote and connect ports automatically
• Control default values for each object
• Database objects easily extended

>> Read more about Beach Solutions Data Capture.

Configurable IP

Share IP across organizations/projects by using generic IP in different systems or derivatives. Optimize the design, as numeric attributes within EASI SoC and EASI Core are parameterized so that values can be overridden when IP blocks are located in a particular system or subsystem.

Use EASI SoC Power to auto-generate RTL for each parameterized IP block in the entire design, where parameterized values are resolved. Alternatively, generate RTL register descriptions for a standalone generic IP block at the click of a button, and generic values are used.

Automated data checking

EASI SoC contains an automated and repetitive data checking process with many system and IP block design rule checks. There are over 250 built-in standard system and IP rules available in EASI SoC, which can be modified with EASI Developer Suite. The types of system and IP block checks are:

• Naming convention conformance e.g. pattern matching, uniqueness
• Memory map address conflicts
• Overlapping items
• Conflicting attributes, e.g. access mode conflicts, data width conflicts

An intuitive graphical user interface presents the errors, warnings and messages in a user-friendly format from which the user can double-click straight to the source of an issue.

Upon a successful data check, the system and its IP blocks are watermarked for added security. Generator-specific watermarks identify known good systems and IP blocks ready for auto-generation for use downstream with the Beach Solutions EASI Tools Suite.

 

Key features

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	EASI SoC	EASI SoC Advanced	EASI SoC Power
Platform (system) data management
Centralized system database based on a language neutral solution
Describe multiple interconnecting system data buses
Locate IP and subsystems in a system bus
Describe external bus master and slave interfaces
Describe ports for external interfaces
Describe net connections for internal and external interfaces
Rapid data creation
Boilerplate templates for common objects
Copy and paste from spreadsheets
Graphical views
System block diagram
Interactive system bus connectivity builder
Interactive system net connectivity builder
Hide/rename objects/attributes in the display
IP configuration
Override parameterized numeric IP values
Data manipulation
Automated method for connecting component ports
Control default values for new objects
Recursive find & replace
Database objects easily extended
Database information reports
Automatic Design Rule Checks (DRC)
> 250 built-in system design rule checks
Graphical presentation of data check results
Double-click straight to source of errors
Save report in textual format
System & IP database watermarked for security
RTL auto-generation
Verilog/VHDL description of bus logic block (each slave interface)
Verilog/VHDL description of address mapped register block
Verilog/VHDL description of memory interface signals with various configurations
Verilog/VHDL description of address decoder
Verilog/VHDL description of read data multiplexer block
Verilog/VHDL description of MRB top level entity & architecture
Enumerated IP block package file
System address map file
Verilog/VHDL description of IP top level
Simple PVCI interface
Customizable bus logic component
Default AMBA AHB and APB bus logic templates supplied
Parameterized IP with instance based generation
Exclude memory mapped registers from register block (resides in IP)
Support for registered read only registers
Support for external reset sources
Support for internal & external enables
Support for set / clear (sticky) bits & self clear bits
Support for double output stage register/bitfields
Support for making write enable signals available externally
Generation of asynchronous or synchronous reset code
Support for registered read enable decodes
Support for registered read mux output stages
Support for alternative clock and/or alternative reset
Exclude reserved objects
Customization of header & footer
Support for single register with different read address and write address
Disconnect register write output from IP
Generator-specific design rule checks to avoid synthesis errors
Documentation auto-generation
Auto-generated HTML design document
Auto-generated RTF design document
Auto-generated PDF design document
Auto-generated MIF design document
Auto-generated HTML memory map document
Auto-generated RTF memory map document
Auto-generated PDF memory map document
System design value comparison
Difference values between two system databases
Graphical navigation of difference results
Double-click straight to source of change
Operating system support
Microsoft® Windows® 2000 / Microsoft® Windows XP®
Red Hat Enterprise Linux AS release 3
Sun Solaris Operating Environment 8

EASI SoC Advanced

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EASI SoC Advanced includes the auto-generation of both printed and web-based documents leading to substantial productivity increases. These automatically generated documents can be updated at the push of a button and then used or distributed as document files or postings to an intranet web site before coding has even started. This simple yet powerful update mechanism ensures that all members of a development team are synchronized and using the latest information as they execute their part of the design.

EASI SoC Power

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EASI SoC Power offers RTL design file auto-generation for each IP block bus interface and local decode for every register and embedded memory in the system. Major quality improvements are achieved using auto-generation as bitfield or register address errors are eliminated and specification misinterpretation errors are avoided.

EASI Developer Suite

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EASI Developer Suite (EDS) includes the Generator Configuration Kit used to modify each of the generators for rapid customization of the structure and content of an auto-generated view. This enables the generators to be customized to support proprietary design flows and improves control over the usability and integration of EASI Tools and Generators within your flows. For example, the design rule checks provided with EASI Core can be tailored and extended to enforce internal constraints and policies.