The Beach Solutions® EASI Tools Suite™ is a sophisticated
and extensible set of Electronic Design Automation (EDA) tools
targeted at increasing the productivity of different key disciplines
within SoC and system integration teams. The EASI Tools Suite
provides the following:
As a semiconductor IP designer you will likely be very busy
performing some if not all of the tasks below:
- IP Architecture
- RTL creation
- Creation of the Programmer’s Model
- Creation of the IP Design Documentation
- Providing IP Source Code and Documentation to System Integrators, Software Developers and Verification Engineers
Within the EASI Tools Suite, Beach Solutions provide products
that will not only automate the generation of many of these
components, but will also streamline other aspects of your
daily work as well.
Within the EASI Tools Suite, EASI Core provides the engineer
tools to capture IP core register data, validate the data’s
correctness against standard and customized rules before storing
this data within the Beach database for further use downstream
in the SoC development process. At this point the IP core
is considered “packaged” for delivery and use
within designs.
Also within EASI Core, the engineer can navigate the register
set of the core and use an interactive bit field graphical
interface and interactive address map viewer to access, modify
and add register and memory information. IP Block ports and
bus interfaces are also defined here.
EASI Core Address Map Viewer
As a semiconductor system integrator you will likely be
very busy performing some if not all of the below tasks:
- Development of the system architecture
- Integrate IP and Systems within Systems (internal and
3rd party IP)
- Creation of System Design Documentation
- Providing Integrated System Source Code (RTL, 'C'. 'e')
and Documentation to Software Developers and Verification
Engineers
Within the Beach Solutions EASI Tools Suite, we provide products
that will not only automate the generation of many of these
components, but will also streamline other aspects of your
daily work as well.
EASI SoC, within the EASI Tools Suite, provides System Integrators
with an application to intuitively build, maintain and reuse
system and sub-system designs using a full graphical approach.
EASI SoC also enables System Integrators to integrate IP at
the system level, describe buses, point to point connections
and create the system level memory map assigning base addresses
to sub-systems and IP.
Within the EASI SoC intuitive graphical user interface, the
SoC integrator can navigate from the top-level block connectivity
diagram all the way down the hierarchy to a particular bit
field in the smallest peripheral at the lowest end of the
hierarchy. As the engineer traverses the architecture register
related information is shown and revealed enabling them to
quickly make modifications, additions or check coherency with
the original design intent.
As the architecture is created, usually in an iterative way,
system memory maps are automatically created for distribution
to software teams. Also, as new cores are added to the design,
RTL for a particular bus interface is automatically generated
to interface the new core to the bus infrastructure.
EASI SoC Bus Connection builder
Configurable IP
Beach Solutions EASI SoC is particularly suited to parameterized
or configurable IP cores and SoC architectures. As particular
attributes are captured within the EASI database as configurable,
EASI SoC automatically resolves parameters as the core is
instantiated within the design.
| Verification
Engineer |
Top |
As a semiconductor verification engineer you will likely be
very busy performing some if not all of the below tasks:
- Development and integration of Verification IP and test
benches
- Verification of Systems including the Entire Chip/Platform
- Communicating Errors to IP Designers and System Integrators
Within the Beach Solutions EASI Tools Suite, we provide products
that will not only automate the generation of many of these
components, but will also streamline other aspects of your
daily work as well.
The Beach Solutions EASI Verification provides a verification
and validation environment tailored to remove labor intensive
and error prone tasks involved in each phase of the design
and integration flow.
Throughout the highly iterative process of design, the Beach
Solutions EASI Tools Suite database maintains a consistent
and up to date model of all of the registers and memories
within the design and their associated information. From this
database EASI Verification auto-generates views and models
used to:
- Integrate verification test benches for the Cadence®
SpecMan-elite® verification engine
- Validate registers and memories using tests in C
- Configure In-Circuit-Emulators (ICE) for SoC and system
debug
In addition, the EASI DRC engine will ensure that IP used
in a design is clean before you start verifying the functionality
of the design itself. Also, within the Advanced package of
the EASI Tools Suite generators are included to auto-generate
design documentation that can be used to distribute information
and communicate changes and remarks to the rest of the team
either as documents or web pages.
As a semiconductor software developer you will likely be very
busy performing some if not all of the below tasks:
- Creation of Register Access Functions (low-level software)
- Creation of Programming Software
- Creation of Software Applications
- Creation of Address Map Documentation of IP and Systems
- Communicating Errors to IP Designers and System Integrators
Within the Beach Solutions EASI Tools Suite, we provide products
that will not only automate the generation of many of these
components, but will also streamline other aspects of your
daily work as well.
EASI Code accelerates the system integration stage as the manual error-prone integration and software layer tasks are automated. Auto-generation of correct-by-construction ‘SystemC’ PV models and ‘C’ API code shortens the software development and test cycle, e.g. register models are available earlier.
EASI Code also presents to the software
developer a graphical canvas upon which flow charts are created
using universal flow chart symbols to construct logical descriptions
of the programming sequence of the SoCs registers and integrate
low-level software API’s. This tool enables to the software
developer to intuitively build, maintain and reuse sequences
using a graphical and text-based approach.
Once register sequences are captured, EASI Code checks
each sequence against an extensible set of rules, and then auto-generates
the associated C code - correct by construction and
ready for delivery and system integration.
EASI Code register flowchart builder
