Auto-generate
Cadence® Specman-Elite® 'e' code
A verification
generator is included within EASI Verification that automatically
produces register and memory package definitions (formerly vr_ad)
in 'e' from the central register-centric database. Generated
files are compatible with the IEEE 1647 standard for ‘e’.
Accelerate verification setup
Each register file and memory can be instantiated under a unit
in the Cadence Specman-Elite® verification environment and
models the behavior of memory and registers. Output file models
can be instantiated within either:
- Module eVC
- XBus environment
- Passive slave agent
Auto-generate C-based integration tests
Bring C test production under control by auto-generating 8-bit,
16-bit, 32-bit and 64-bit to fully exercise the IP address mapped
register and memory interface. The same tests can be run in
pre and post silicon, in simulation and on real hardware.
Comprehensive test coverage
Each test can be compiled and run separately to form part
of a larger HDL testbench:
- Read-only register tests and write-only register tests check
that registers can be accessed correctly
- Register power on reset tests check default values for each
register
- Register write and then read tests to check the integrity
for each register
- Register POR, write and read tests to check the exclusivity
behavior for each register
- Memory write and then read tests to check the integrity
for each area of memory
- Additional stepped tests to test memory integrity at specified
intervals
- Supporting default type definitions
Write tests are easily configured with user-defined test
patterns.
Each test contains calls to message macros to output different
messages during the test and is specifically designed to minimize
any unnecessary transactions while allowing for full debug
of the results. EASI Verification includes an example Perl
script to translate a message file into a human readable log
file, allowing system integrators to focus on checking functional
design rather than debugging the system interfaces.
Auto-generate HDL testbench
IP designers use the auto-generated RTL files as a self-checking
verification environment for rapid IP block interface
testing before system integration occurs. The auto-generated comprehensive verification environment can be used to test:
- Synthesizable RTL output from the Beach Solutions Standard Verilog MRB generator
- Synthesizable RTL output from the Beach Solutions Standard VHDL MRB generator
- A programmer's view model output from the Beach Solutions Standard SystemC PV Model generator
Providing a jumpstart to IP verification, the auto-generated
Verilog test harness contains extendable APIs to drive any
MRB (DUT), model interface-transactions (system bus
read/write), and monitor the MRB output. Sample setup scripts
are provided for Cadence® Incisive® and Mentor Graphics
ModelSim®. Use with the Beach Solutions Verilog/VHDL MRB
generator or SystemC PV Model generator.
Auto-generate
Lauterbach TRACE32 configuration files
Auto-generate a single .PER file for the entire system or
a separate .PER file for each peripheral to configure the
Lauterbach ICE TRACE32 debugger containing:
- Register names mapped to memory locations
- Full bitfield detail
- Hardware design enumerated values
Output is target-independent and works for all TRACE32 compatible
targets, models, development boards and final systems.
